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Cadence-Allegro-PCB-SI
利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)
- 2013-08-06 22:17:46下载
- 积分:1
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FPGA PWM输入与输出
自己写的pwm占空比采集与输出 但是没有计算占空比,如果又需要可以自己修改计算并显示占空比,该程序已经测试过了,可以使用,拿出来供大家分享,新手写的如有不足请大牛带飞。
- 2022-01-28 02:10:47下载
- 积分:1
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Flash接口控制器的VHDL和Verilog源代码和程序测试
flash接口控制器的VHDL以及verilog源代码和Testbench程序-flash interface controller VHDL and Verilog source code and procedures Testbench
- 2022-06-27 08:57:14下载
- 积分:1
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a_sistolic_FFT_architecture_for_FPGA
Description of a sistolic arhictecture for a FFT implementation in FPGA.
- 2009-03-24 18:12:27下载
- 积分:1
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train_controler
train controler by verilog
- 2012-09-03 16:16:23下载
- 积分:1
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i2c
说明: I2C完整代码,可综合,可仿真,已经过验证(I2C code can been syn and simulation ,veritify)
- 2021-02-26 13:11:46下载
- 积分:1
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multifre
说明: 资料的内容是实现旋转机械同步整周期采样的数据采集系统相关文献资料,包括鉴相信号如何倍频,机械振动信号相位如何检测等的实现方法。(Information content is for rotating mechanical synchronization synchronous sampling data acquisition system-related documents, including the Kam-believe number to harmonic mechanical vibration signal phase to detection of realization.)
- 2010-04-26 15:56:20下载
- 积分:1
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add_noisem
把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92,其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等,在信号处理中往往需要把库中的噪声叠加到信号中去,而噪声的采样频率与纯信号的采样频率往往不一致,需要采样频率的校准。
(The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)
- 2012-08-10 14:18:33下载
- 积分:1
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FPGA_DSP
《FPGA数字信号处理与工程应用实践附光盘》配套源代码(FPGA DSP and their applications with verilog HDL)
- 2020-07-01 16:00:01下载
- 积分:1
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This application note explains the process of eveloping and debugging a hardware...
This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.
- 2022-01-23 11:16:04下载
- 积分:1