基于FPGA的VHDL可以产生不同的音调,象音乐一样

使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)

这里面有很多的vhdl的编程的源代码，文件是全英文的，例子丰富(That there are a lot of vhdl programming source code, documentation is in English, and examples of rich)

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)

用verilog语言编写的步进电机加减速控制算法，可选择梯形曲线或S型曲线算法(Verilog language stepper motor acceleration and deceleration control algorithm, you can choose the trapezoidal curve or S-curve algorithm)

自己编的VHDL的波形发生器 做信号的可以-BOXING

5分代码及说明，verilog代码，几乎所有的IC面试都会问到这个问题，所以总结了一下发了上来，共同学习！-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!

project proposal of verilog language that is gud for beginners

含移动储能的分布式电能优化调度，模型的处理与改进(Processing and improvement of distributed power optimization scheduling with mobile energy storage)

出租车的计费功能的实现,计量模块、计费模块、控制模块、译码模块。(taxi fee)

AD采集模块,设计模块采集AD5270的输出数据(AD Collection module Design module to collect the output data of AD5270 )