xilinx the frequency generator VHDL source code, spartan3 can run in the learnin...

基于PID 控制算法的直流电机控制，输出PWM波，很容易用(motor control)

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

该实验完成的功能是STM32与FPGA通信(The function of the experiment is STM32 and FPGA communication)

本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输，实现了pc端接收来自FPGA开发板的数据，并显示条纹，具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)

HDLC通信协议，FPGA实现，包含源文件和仿真测试文件。(HDLC comunication)

逆变器并网发电的主要是逆变器输出正弦波电流的控制技术，要求与电网同频同相的电流，此matlab模型中使用锁相环技术，恒功率控制，LCL滤波器技术使达到并网要求(Constant_PQ_Microgid )

fault minimization using genetic algorithm

基于PCI的数字信号发生器 关键词：PCI总线，PCI9054，FPGA，卡尔曼滤波器(PCI-based digital signal generator Keywords: PCI bus, PCI9054, FPGA, Kalman filter)

alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)