FPGA SDRAM with the operation of the specific see internal note

说明：  数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

Testbench 不仅要产生激励也就是输入，还要验证响应也就是输出。当然也可以只产生 激励，然后通过波形窗口通过人工的方法去验证波形，这种方法只能适用于小规模的设计(The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method is only applicable to small-scale design)

利用VHDL实现CPLD（EPM240T100C5）的串口接收程序-Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure

说明：  基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)

资源描述这个秒表特点是计数到59分59秒9，并且有可以让计数暂停和清零。采用了二分频，六进制和十进制组合，加上扫描电路设计而成的。

BCD码减法实现程序，非常完整，采用Verilog HDL语言实现。(BCD subtraction to achieve program code, very complete, using Verilog HDL language.)

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)

说明：  SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)

UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列 UG C program，homework，student，study，first，hole，complex，many( UG C program，homework，student，study，first，hole，complex，many)

基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!