sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制...

说明：  document qpsk vhdl code

Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be

等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)

说明：  misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

数码管显示有片选 模块 四输入，与其他模块相连即可使用-digital film of the election showed that four input modules, and other modules can be linked to the use of

ieee paper on power gating and can be use full for implementing on ip core

Aurora协议是一款高带宽、低成本、可扩展、框架简洁、适合点对点串行数据传输的协议。(Aurora protocol is a high-bandwidth, low-cost, scalable, simple framework for point to point serial data transfer protocol.)

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

篮球24s计时器，元器件简单，功能复杂。满足小型计时需要。