sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制...

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

sub opercore USB CRC5 and CRC16 Modules //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)

I2C总线在可编程逻辑器件上实现的VHDL源码-VHDL source codes for realizing I2C

基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)

axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)

LabVIEW FPGA SPI implementation

ADC TLC5510的测试程序，经过测试通过，十分简单好用-ADC TLC5510 test procedures, after the test is very simple and easy

XAPP585 serdes_1_to_7 and serdes_7_to_1 data

vhdl

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)