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uart
UART串口的verilog源代码,完全正确...........(UART serial Verilog source code, completely correct ...........)
- 2009-03-02 14:44:16下载
- 积分:1
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ComunicationRealizationBetweenFPGAandSerialInterfa
说明: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议,给出了发送模块的vhdl源代码。
(杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)
- 2008-11-18 15:41:34下载
- 积分:1
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FPGA PWM输入与输出
自己写的pwm占空比采集与输出 但是没有计算占空比,如果又需要可以自己修改计算并显示占空比,该程序已经测试过了,可以使用,拿出来供大家分享,新手写的如有不足请大牛带飞。
- 2022-01-28 02:10:47下载
- 积分:1
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hex_counter-2014-10-15
hex_counter
old project, please let me know if need any help
- 2014-12-03 02:21:05下载
- 积分:1
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bianyuanjiance
说明: 图像采集 VGA输出 图像的边缘 ov7670(V image acquisition VGA output image edge)
- 2020-06-21 13:20:06下载
- 积分:1
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VHDL version of the C8051 core (C8051). Evatronix company s IP core
VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
- 2022-09-22 12:10:03下载
- 积分:1
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一个简单的移位寄存器。VHDL语言的,或许会对你有所帮助!
一个简单的移位寄存器。VHDL语言的,或许会对你有所帮助!-A simple shift register. VHDL language, and perhaps will help you!
- 2023-07-05 13:15:03下载
- 积分:1
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加法计数器的VHDL工程,程序,仿真图形
加法计数器的VHDL工程,程序,仿真图形-adder jishuqi de VHDL FANGZHEN ,CHENGXU
- 2022-01-25 14:28:29下载
- 积分:1
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suzimiaobiao
数字秒表的实现,我还写个具体的过程要求等,(there is function of clock,it very useful)
- 2011-09-20 14:28:30下载
- 积分:1
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HOWTO_-Get-Configuration-and-Location-Information
this document used for how to get config and location information of PCI card
- 2012-07-21 12:26:16下载
- 积分:1