计数器的VHDL语言程序实现1

this is a Multiplier and Accumulate (MAC). written in VHDL

数控分频器的输出信号频率为输入数据的函数。用传统的方法设计,其设计过程和电路都比较复杂,且设计成 果的可修改性和可移植性都较差。基于VHDL 的数控分频器设计,整个过程简单、快捷,极易修改,可移植性强。他可利用 并行预置数的加法计数器和减法计数器实现。广泛应用于电子仪器、乐器等数字电子系统中。-NC divider output signal frequency is a function of input data. Using traditional methods of design, process and circuit design are complex and can modify the design of the results are poor and portability. NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability. He can use preset number of parallel addition and subtraction counter counter to achieve. Widely used in electronic equipment, musical instruments and other digital electronic systems.

it performs the floating point arithmetic unit

基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `

利用c控制adc，主要是控制字写入，状态控制。-C control the use of adc, is mainly controlled write, the state of control.

VCP201_CODE is a FPGA source code.

Xilinx FPGA reset usage

FPGA开发PCIe的源码，采用VHDL语言，通过此源码，能更好的掌握PCIe总线，使开发者少走弯路，

说明：  uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device