它执行浮点运算单元

Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles

在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)

vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)

FPGA读写SDRAM的VHDL程序(已经测试过)-SDRAM read and write the VHDL program FPGA (already tested)

VHDL BASED DATA COMPRESSION

这个是一个基于FPGA的SDRAM控制器系统，实现对SDRAM的读写操作，用来实现时序的控制-This is an FPGA-based SDRAM controller system, the read and write operations to SDRAM to achieve the control of timing

读取AD7895 的12位ADC转换值，连续读取方式，采样速率为20mS 一次。(Read the 12 bit ADC conversion value of AD7895.)

3-8译码器地简单实现，采用QUARTUSii5.0环境编译-3-8 decoder to realize a simple, using the compiler QUARTUSii5.0 environment

关于FFT算法的FPGA实现（源码），数字信号处理不可少。-FFT algorithm on the FPGA implementation (source code)

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )