virtex7_pcie_dma

An odd parity checker as an FSM using VHDL

这是关于赢vhdl语言变得信号采集卡，很有实用性，大家可以来看看的。-This is about winning VHDL language has become signal acquisition card, is very practical, we can take a look at the.

使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

RobustVerilog生成verilog工具(RobustVerilog version)

基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)

串行数据开发实用代码， 适合初级学习者使用 很不错(Serial data to develop a practical code for primary learners use very good)

RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].

以上是VHDL硬件描述语言写的一个简单锝路流水灯程序,希望对刚接触VHDL的朋友有一定帮助-These are the VHDL hardware description language written in a simple flow path lights technetium procedures,刚接触VHDL want to have some friends to help

here is gangadhar call by mailing me

说明：  quartus的破解软件，里面有说明文档(Quartus crack software, which contains documentation.)