vcp201_code是FPGA的源代码。

FPGA课件，个人感觉不错，希望对大家有帮助(FPGA software, personal feel good, I hope all of you help)

PC104总线的CPLD代码，调试已经通过，可以修改应用到其他的工程(PC104 bus CPLD code, debugging has been passed, you can modify the application to other engineering 示例用法:)

Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。 (Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)

This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.

Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim

5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态(dianti in verilog)

This is counter with T_FF.

有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.

IT8051，增强版的T51，兼容DW8051核的多数端口，IO需要扩展后使用