this come from alter ,you can look and find it on line about USB

用FPGA实现SPWM波输出，其中包含三角波和正弦波(With the FPGA realization of SPWM wave output, including triangle wave and sine wave )

个人搜集的各类Modelsim教程全集视频PDFWordPPT等.rar(Personal collection of all kinds of Modelsim tutorial video PDFWordPPT Complete Works, etc.. Rar)

Computer Architecture Handbook on Verilog HDL

64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)

verilog支持noise噪声的端口port, 可以用于仿真运行. 评估噪声影响 Verilog port that supports noise and can be used for simulation run. Evaluate noise effects

RS译码的Euclid算法及其FPGA实现，并通过仿真器的出结果，对于设计ＲＳ译码很有帮助-RS decoding Euclid algorithm and its FPGA implementation, and through the simulator results are helpful for the design of RS decoder

说明：  ertyguhijop[lkjhvbn hiouopi][[poiuy

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

使用VHDL进行分频器设计，主要是一些分频的东西，整数分频，小数分频，奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency

这份代码完成的功能是通过蜂鸣器播放《梁祝》这首曲子，当然可以自行更改代码，以播放其它的乐曲，所用的硬件描述语言是VHDL，代码有四部分构成，顶层模块、预分频模块（产生基频）、音乐表格和分频模块（产生所需的各音调）。