计算机体系结构手册上的Verilog HDL

用Quartus II开发的一个十进制计数器，包括仿真波形，下载文件，是完整工程。(With the Quartus II development of a decimal counter, including the simulation waveform, download files, is the complete project.)

SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用(SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses)

xilinx ise开发环境中fft IP核调用，仿真(Xilinx ise development environment FFT IP core call, simulation)

通信系统帧同步信号的设计与实现，巴克码识别器系统完整VHDL程序，本人课程设计，完全能正常运行，程序运行环境为Quartus II 7.2 (32-Bit)，win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流，共同学习！！

一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code

利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )

135个经典VerilogHDL源码和说明文档，入门的好资料-135 Classic VerilogHDL source and documentation, a good data entry

very nice program that i ensure anyone can use easily and will be efficient for hard project of elevator

verilog source code for SD card SLAVE DEVICE IP-Core

利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.