用VHDL语言设计分频器，主要是因为一些子

分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.

一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation

数字钟VHDL软件设计，包含多种功能，报时，12,24切换，调时(The design of VHDL digital clock software, including a variety of functions, timer, 12,24 switch, adjustable)

This is the Spartan 3E tutorial_02.

王金明：《Verilog HDL 程序设计教程》程序-Wang Jinming:

1024点FFT快速傅立叶变换,(vhdl代码)-1024-point FFT vhdl

SPI接口的实现以及对外设的读写操作，其中包扩了几种工作方式，同时可以读取外设的版本号，传输速率可以达到2Mbps-SPI interface implementation, as well as read and write operations on the peripheral, which extended several work packages at the same time can read the version number of peripherals, transfer rate up to 2Mbps

沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)

8倍抽取的DDC模块。verilog写的，调试通过(failed to translate)

有关于SD卡的音频部分！希望对大家有用！-SD cards have on the audio portion! Hope useful for everyone!