登录
首页 » VHDL » verilog支持noise噪声的端口port

verilog支持noise噪声的端口port

于 2022-07-25 发布 文件大小:1.31 kB
0 151
下载积分: 2 下载次数: 1

代码说明:

verilog支持noise噪声的端口port, 可以用于仿真运行. 评估噪声影响 Verilog port that supports noise and can be used for simulation run. Evaluate noise effects

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • PAL_VGA
    基于FPGA的PAL_VGA转换器的实现.pdf(FPGA-based PAL_VGA converter implementation)
    2009-03-17 14:13:36下载
    积分:1
  • DecimationFilterDesignforDDCandImplementingItwithF
    本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性(This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design)
    2008-04-14 11:02:00下载
    积分:1
  • utmi
    介绍USB PHY接口中的UTMI接口, 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)
    2021-03-17 21:39:21下载
    积分:1
  • 1
    说明:  一个解决除法溢出的例子,可以学习到很多,注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
    2013-12-24 09:19:13下载
    积分:1
  • 有关FPGA芯片的管脚的封装的一些资料。
    有关FPGA芯片的管脚的封装的一些资料。-Pin on the FPGA chip packaging some of the information.
    2023-06-26 06:30:03下载
    积分:1
  • msk的verilog程序 利用FPGA实现
    msk的verilog程序 利用FPGA实现-MSK procedures for the use of Verilog FPGA realize
    2022-03-12 22:28:22下载
    积分:1
  • 华为经典FPGA设计全套入门技巧
    华为经典设计全套入门技巧,面试经验,设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)
    2020-07-01 23:00:02下载
    积分:1
  • 小梅哥RTL8211PHYFPGA
    说明:  基于RTL8211以太网芯片开发的以太网通信代码,使用Quartus编程,FPGA板子为开发者(Ethernet communication code based on rtl8211 Ethernet chip, using quartus programming, FPGA board for developers)
    2020-09-17 21:47:55下载
    积分:1
  • PC
    说明:  Verilog HDL语言编写的32位程序计数器(PC)完整工程及相应仿真,QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)
    2012-09-06 09:07:47下载
    积分:1
  • DE0_Nano_SOPC_DEMO
    Altera DE0-Nano 开发平台SOPC可编程片上系统实现官方Demo。(Altera DE0-Nano development platform the SOPC programmable on-chip system Official Demo.)
    2013-03-18 06:16:13下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载