以VHDL为第一通用代码的N位加法器

文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.

Dynamic Power Management for the Iterative Decoding of Turbo Codes

用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)

基于单片机与CPLD的 等精度频率计，VHDL语言-Based on SCM and CPLD

基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)

宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)

altera 的reed solomn 设计(reed solomn design from altera)

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

DEMO中完成WIAGAND26/32的（EMP7128实现）协议程序源代码-DEMO completed WIAGAND26/32 (EMP achieved) agreement procedure source code