VHDL实现CDMA

VHDL语言写的频率计的程序，内带完整的技术报告-VHDL write the frequency of procedures, brought integrity of the technical report

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)

用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.

早迟门（early late gate），比特同步算法，该文档详细的说明了早迟门算法的原理以及具体的实现步骤(Early late gate (early late gate), bit synchronization algorithm, the document explains in detail the principles of early-late gate method and the specific implementation steps)

RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

本资源包括了加法器的VHDL代码实现，供大家学习。

说明：  1、SignalTap II Logic Analyzer使用方法； 2、掌握捕获条件的设置 3、学会硬件信号分析，了解硬件信号监视和软件调试的差异(1. How to use signaltap II logic analyzer; 2. Master the setting of capture conditions 3. Learn hardware signal analysis, understand the difference between hardware signal monitoring and software debugging)

使用VERILOG开发时钟同步算法，能够从数据信号中提取时钟信息，(Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,)