Altera DE2板专用CCD驱动器

可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。可实现任意频率的LED点灯形式，只需改变分频次数和赋值就可以得到想要的的结果。

mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过 (mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)

高速FIFO，verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)

URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器，也包括用来完成数据运算的组合逻辑电路单元。控制单元用来产生控制信号序列，以决定何时进行何种数据运算。控制单元要从数据单元得到条件信号，以决定继续进行那些数据运算，数据单元要产生输出信号，数据运算状态等有用信息。-URISC processor by the data unit and control unit. Data unit included in the preservation of data and computing the results of computing the data register, but also data used to complete a combination of computing logic circuit unit. Control unit used to generate the control signal sequence, to determine when and what data computing. Control unit from the data unit received condition signal to determine the continuation of the data computation, data unit to produce output signals, data, such as computing the state of useful information.

一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)

说明：  AMBA2.0标准的AHB2APb桥，代码通过验证(AMBA2.0 standard AHB2APb Bridge, through the verification code)

LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language

控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.(Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.)

fpga Verilog 控制读写flash (fpga Verilog flash )

verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)