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hdl_adder
MATLAB to HDL Code conversion
- 2020-06-17 12:40:01下载
- 积分:1
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ba_ker
巴克码装到信息内同时将巴克码识别出来,实现帧同步的VHDL设计(Barker code loaded to the information identified while Barker code, VHDL design to achieve frame synchronization)
- 2014-05-18 17:37:39下载
- 积分:1
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LVDS-application-Verilog-HDL-code
LVDS的应用的Verilog HDL例子程序(LVDS example of the application procedures for the Verilog HDL)
- 2011-09-30 20:24:02下载
- 积分:1
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iic_sci
FPGA编程,经过团体奋战完成,全是底层的IIc和sci通信,完整版。(FPGA programming, after groups fight to the finish, all underlying SCI and IIc communication, full version)
- 2014-12-23 09:32:54下载
- 积分:1
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本设计可直接用作时钟计数器
本设计可直接用作时钟计数器,同时有调时,定时功能。 Led[3:0]显示秒钟的变化情况。 func用作计时,调时,定时功能转换。 Ledarrive用于提示计时时间已到。 change可使秒钟在数码管显示。 plus键在调时计时时使时钟加一。 shift用于调时计时时分计时与时计时的调整转换。
- 2022-12-28 21:25:04下载
- 积分:1
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protel fpga library a popular package is very difficult to find the
protel fpga常用封装库1,非常难找的-protel fpga library a popular package is very difficult to find the
- 2023-04-26 17:30:02下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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关于寄存器重命名register reallocation,VHDL
关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
- 2022-02-09 20:31:31下载
- 积分:1
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practica1
binary comparator with register
- 2012-04-24 17:39:04下载
- 积分:1
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用Verilog 实现的电子时钟,给初学者一个模版,学习Verilog。
用Verilog 实现的电子时钟,给初学者一个模版,学习Verilog。-Using Verilog realize an electronic clock, a template for beginners to learn Verilog.
- 2022-03-01 20:04:47下载
- 积分:1