一个FPGA的AVR_Core 仅供测试~

自己编的VHDL的波形发生器 做信号的可以-BOXING

基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)

数字电子钟用自拍图像代替了内置图像的石英制作

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!

说明：  一个红外遥控，可以学习其他的红外编码，并存储记忆，并且将学习到的编码发送(An infrared remote control)

VHDL教程及源码,是新手入门的不二选择!-VHDL Tutorial and source code is the only option, beginners!

自己用verilog编写的urisc程序，调试成功，压缩包里有仿真图像，值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

vhdl,双向移位寄存器，实现置数，左移及右移操作-vhdl, bi-directional shift register to achieve set the number of left and right shift operation