自己编的VHDL的波形发生器 做信号的可以

基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)

4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.-4. If a modified source code is distributed, the original unmodified-- source code must also be included (or a link to the Free IP web-- site). In the modified source code there must be clear-- identification of the modified version.

mux2to1.vhd二选一电路mux2_1.vhd二选一电路mux2_1.bdf二选一电路mux3to1.vhd三选择电路mux3to1_1.vhd三选一选一个电路mux4to1.vhd 4

verilog实现的数字跑表 精确到10ms-verilog digital stopwatch to achieve accurate to 10ms

一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.

usb3.0 物理层仿真，verilog编程(Start the physical simulation)

资源描述VGA视频图形阵列（VGA）接口是一三排15针de-15连接器。15针VGA接口是许多视频卡，发现电脑显示器，以及一些高清晰度电视机。在笔记本电脑或其他小型设备，迷你VGA端口有时用于全尺寸的VGA接口的地方。

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE

说明：  8通道24Bit同步A/D芯片AD7768的SPI接口例程(SPI interface routine of 8-channel 24bit synchronous A / D chip ad7768)

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)