自己编的VHDL的波形发生器 做信号的可以

vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)

时钟在单片机中的应用，用于控制中断及显示程序(Clock in the MCU application, used to control interrupt and display program)

可用的24位x24位的booth乘法器的verilog代码(24X24 booth muplily)

有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace tree Final stage addition: Carry select adder )

说明：  DAC3283 寄存器初始化，SPI驱动(Dac3283 register initialization, SPI drive)

design a clock using KIT DE1

各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format

使用飓风开发板，完成了100M，频率计设计，并可在数码管显示

1024点fft verilog hdl(1024-point fft verilog hdl)

在matlab中8psk的调制和解调仿真程序(the modulation and demodulation of 8psk)