is done in the laboratory in the loss of 60 counts, and LED show.

QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)

一些简单的Verilog代码，小例程，比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)

应用背景建筑行为是counterled恒clk_50mhz_freq：整数：= 50000000；恒blink_freq：整数：= 1；恒cnt_max：整数：= clk_50mhz_freq / blink_freq / 2 - 1；恒blink_freq2：整数：= 8；恒cnt_max2：整数：= clk_50mhz_freq / blink_freq2 / 2 - 1；恒cnt_max3：整数：= clk_50mhz_freq / blink_freq * 2 - 1；信号CNT：符号（24到0）；信号CNT2：符号（22到0）；信号cnt3：符号（27到0）；信号闪现：std_logic：=“1”；信号trigger_s：std_logic：=“0”；信号enableblink1s  ；：std_logic：=“0”；开始过程（clk_50mhz）开始 ； ；如果（clk_50mhz = 1”和clk_50mhz"event）然后 ； ； ； ；trigger_s & lt；=触发；如果（不trigger_s触发）=“1”，然后enableblink1s & lt；=“1”；cnt3 & lt；=（别人= & gt；0）；如果结束；如果enableblink1s =“1”，然后如果CNT2 = cnt_max2然后CNT2 & lt；=（别人= & gt；0）；眨眼和不眨眼；其他的CNT2 & lt；= CNT2 + 1；如果结束；如果cnt3 = cnt_max3然后cnt3 & lt；=（别人= & gt；0）；enableblink1s & lt；=“0”；其他的cnt3 & lt；= cnt3 + 1；如果结束；还有其他的；如果碳纳米管= cnt_max然后CNT & lt；=（别人= & gt；0）；眨眼和不眨眼；其他的碳纳米管和碳纳米管+ 1；如果结束；如果结束；和，结束如果；和；结束过程；awake_led & lt；=眨眼；结束行为；关键技术图书馆的IEEE；std_logic_1164.all；std_logic_unsigned.all；numeric_std.all；counterled是端口（

用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.

fifo程序代码，程序编写，测试仿真图形，方便，比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)

(7,4)循环码的verilog编码程序，（7，4）循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)

UART模块的VHDL语言设计(Design of VHDL language based on UART module)

这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)

说明：  designers guide to vhdl(third edition)这本书好像在国外vhdl入门中挺流行的, 爱思维尔有资源,但是是各个章节散装的, 我把它们合成了(The book designers guide to vhdl (third edition) seems to be very popular in foreign vhdl entry. Ixel has resources, but it is a loose chapter of each chapter, I synthesized them)

将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)