-
DDS
文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术,研制和
设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and
Design of high resolution, high stability function of the signal
)
- 2013-08-27 14:20:22下载
- 积分:1
-
007
给大家上传一本非常好的关于verilog-hdl的电子书,实用,易懂,易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)
- 2008-04-22 16:53:33下载
- 积分:1
-
基于FPGA的VGA彩条显示 可用PAXplusII仿真
基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of
- 2022-07-12 22:45:31下载
- 积分:1
-
Avt_S6LX9_MicroBoard_UCF_110127
Avt_S6LX9_MicroBoard_UCF_110127,有关xilinx spartan6开发板的相关参考设计。(Adding Custom IP to an Embedded System, the relevant reference on xilinx design.)
- 2013-07-03 11:26:20下载
- 积分:1
-
jiaotongdeng
交通灯通过数码管显示,几种模式可调,还可以时间可设,适合初学者入门参考学习。(LED traffic lights can be set to several modes adjustable time beginners reference ~ ~ ~)
- 2013-08-25 10:02:34下载
- 积分:1
-
05_key_test
利用FPGA实现对外设按键的控制,例如用户库用按键控制跑马灯的效果(FPGA is used to realize the control of external keys, such as the effect of user database using keys to control the running horse lamp)
- 2020-06-16 10:00:11下载
- 积分:1
-
aaa
这是一些小代码的集合
希望能对大家有所帮助(This is a collection of some small code for all of us hope to be helpful)
- 2007-11-16 06:19:33下载
- 积分:1
-
数字电子设备上下计数器的实现
上/下计数器是有用的大规模集成
- 2022-01-26 01:21:27下载
- 积分:1
-
vhdl
说明: 这个事VHDL基础知识,内面主要内容是编码器的插V过程,值得下载学习!(it is really useful for those who never touch it!)
- 2010-04-16 13:57:35下载
- 积分:1
-
i2c
说明: 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准,以主机模式与外围设备进行数据通信,对IIC从机模型进行读/读,读/写,写/写,写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失,自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分:1