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JTAG_Example0_Verilog
一个Verilog的JTAG程序例子,包括完整的说明文档和源文件。(tap_top.v
This file is part of the JTAG Test Access Port (TAP)
http://www.opencores.org/projects/jtag/
Author(s): Igor Mohor (igorm@opencores.org))
- 2021-04-27 13:48:44下载
- 积分:1
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23
说明: 基于FPGA的液晶显示控制器的设计,FPGA用的是EP2C5,LCD用的是ST7920内核的122*32点阵的LCD,显示中西文字符(FPGA-based LCD display controller design, FPGA is used EP2C5, LCD is used in the ST7920 core of 122* 32 dot matrix LCD, display of Chinese and Western characters)
- 2009-06-19 22:01:23下载
- 积分:1
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8255参考设计VHDL源代码
8255参考设计VHDL源代码-The sound code of 8255 reference design based on VHDL
- 2022-05-31 03:46:31下载
- 积分:1
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asynchronous-fifo
同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分:1
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MID_FILTER
中值滤波算法的verilog实现,可用于相关算法在基于FPGA的嵌入式图像处理系统中。(Median filtering algorithm verilog realization available FPGA-based embedded image processing system.)
- 2015-03-16 19:36:18下载
- 积分:1
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rc6_decryption
rc6 algorithm designed based on verilog and is verified
- 2020-12-01 21:59:28下载
- 积分:1
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使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟...
使用VHDL语言编程,烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
- 2022-06-20 16:23:08下载
- 积分:1
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FFT处理器,FPGA的设计,适用于信号处理技术参考…
FFT处理器的FPGA设计方法,适合做信号处理的技术人员参考,用FPGA实现-FFT processor, FPGA design, suitable for signal processing technology for reference, using FPGA to achieve
- 2022-12-05 04:55:03下载
- 积分:1
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FPGA+AD7656
说明: FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)
- 2020-10-11 23:27:32下载
- 积分:1
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33753129vhdl
对数计算源程序,能够在FPGA中计算某数的对数(Determined on the basis of the source, calculated in the FPGA to a certain number of log)
- 2009-06-17 19:41:57下载
- 积分:1