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Signal
基于FPGA的DDS相位累加器,连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)
- 2018-05-10 15:19:05下载
- 积分:1
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ser_to_parr
很有用的10bit串并转换verilog程序,需要的可以拿去参考下,在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分:1
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超大规模集成电路的VHDL基本编码…………
- 2022-03-26 19:32:17下载
- 积分:1
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VHDL手册很不错,适合硬件描述语言指南
VHDL handbook is very nice and suitable guide to HVDL language
- 2022-04-17 19:38:41下载
- 积分:1
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liushui
本程序实现流水线功能,您可根据自己需要更改参数,试用芯片xilinx,用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)
- 2016-03-07 09:26:28下载
- 积分:1
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一个FPGA的AVR_Core
仅供测试~
一个FPGA的AVR_Core
仅供测试~-AVR_Core an FPGA-only test ~
- 2023-08-16 08:25:03下载
- 积分:1
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fir_lms
基于FPGA的自适应滤波器的实现。采用Verilog编程,2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)
- 2009-04-27 12:06:25下载
- 积分:1
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configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design do...
可配置CRC参考设计 xilinx的ip,参考设计文档CRC_xapp562[1].pdf,VHDL语言编写的代码,包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
- 2022-01-26 00:23:00下载
- 积分:1
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Yoshis_Island_(V1.0)_(U)
Bringing SMW2:YI Back To LIFE Through Rom!
- 2013-01-19 23:40:42下载
- 积分:1
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FIRfilterverilogHDL
FIR滤波器的verilog HDL代码示例,以16阶为例(Verilog HDL code for fir filter)
- 2015-07-08 17:05:38下载
- 积分:1