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vhdl classical source code
vhdl经典源代码――ps2接口设计,入门者必须掌握-vhdl classical source code-- ps2 interface design, beginners must master
- 2022-04-07 18:12:38下载
- 积分:1
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Interpolator-of-polyphase-filter
代码用两种方法设计了一个基于多相滤波的内插器,低通滤波器采用128阶凯撒窗,内插倍数32,并且给定信号范围,验证了内插器的正确性,画出了内插前后信号的频谱。(The code design the interpolator based on polyphase filter using two methods.The low pass filter is 128 order Caesar window and interpolation multiple is 32.I give the range of the signal to verify the interpolator and plot the spectrum of the signal before and after the interpolator. )
- 2021-01-09 13:18:51下载
- 积分:1
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Digital signal source, the output of different frequency, phase is the cosine si...
数字信号源,输出不同频率,相位的正余弦信号,-Digital signal source, the output of different frequency, phase is the cosine signal,
- 2022-04-23 09:40:37下载
- 积分:1
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LMS
least mean square algo implemented on verilog
- 2017-11-01 05:01:56下载
- 积分:1
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CORDIC算法的FFT实现
本代码实现了 ; ;CORDIC ; 算法语言;
- 2022-09-09 16:25:03下载
- 积分:1
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FPGA——IP_RAM实验
说明: FPGA——IP_RAM实验:
创建IPRAM核,单端口,10位地址线(256字节),8位数据线(每字节8byte),读写使能
input [9:0] address;
input clock;
input [7:0] data;
input wren; //置1则写入
output [7:0] q;
LNXmode:控制LEDC显示
1:mode1,从k1~k3输入data的低4位,ledb计时,从0~f,计时跳变沿读取k1~k3的值,存入RAM
8个数之后,从RAM输出数据,用leda显示,同样每秒变化一次(The experiment of FPGA-IP_RAM:
Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)
- 2020-06-22 04:20:02下载
- 积分:1
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vga
VGA interface using Spartan3E board from DIGILENT.Labview .vi
- 2009-09-23 05:02:44下载
- 积分:1
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ADS8509
FPGA驱动高输入电压范围的ADS8509芯片,采样范围广,适合前端大信号处理(FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing)
- 2015-08-10 22:03:59下载
- 积分:1
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基于CPLD的38译码器程序设计
基于CPLD的38译码器程序设计,使用VHDL语言编程,38译码器显示在数码管上。
- 2023-03-14 08:00:04下载
- 积分:1
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06219426Spartan3E
VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)
- 2011-02-10 09:41:12下载
- 积分:1