include UART port of VERILOG source, the program tested in FPGA, as chip design,...

一个时钟程序，还有跑表，感觉相当不错的，有需要就下载吧-A clock procedures, as well as stopwatch, I feel pretty good, there is a need to download it

VHDL operators basics

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

低通滤波器在QUARTUS7.0开发环境下的文本与框图结合的实现方法的源代码-Low-pass filter QUARTUS7.0 development environment in the text and diagram combination of methods to achieve source code

该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间(The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this egg pain)

在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。(Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.)

Xilinx FPGA make 50 smaller-Xilinx FPGA make 50 smaller

基于FPGA的多功能波形发生器,很好的,使用Verilong程序。(FPGA-based multi-function waveform generator, a good use of Verilong program.)

硬件描述语言相关芯片程序源码Chip hardware description language-related program source code(Chip hardware description language-related program source Chip hardware description language-related program source code)

USB+FPGA电路设计原理图，实际的电路板运行正常，很有参考意义。-usb_sch