VHDL的您的信息的一个游戏程序的源代码，我希望那些在…

用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特(Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

SMT32F4 i2s 全双工配置，自己测试OK的，大家可以看看(SMT32F4 i2s 全双工配置)

Altera DE0-Nano 开发平台SOPC可编程片上系统实现官方Demo。(Altera DE0-Nano development platform the SOPC programmable on-chip system Official Demo.)

基于FPGA的PCM编码器与解码器的设计-about fpga and pcm

ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)

说明：  高速流水的SDRAM控制器，最高速度可达速度在200M左右(high speed SDRAM controller)

此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.

verilog code for apb to ahb convert

简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)