VHDL的您的信息的一个游戏程序的源代码，我希望那些在…

说明：  this code works with spi and uart interfaces.

verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)

1553B总线BC端的编程例子，做通了对于一个RT的测试。对于其他的RT测试和程序的例子原理相同。(The BC end of the 1553B bus programming examples)

有关gal器件的编程入门，以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)

DDS_AD9854_for FPGA ,FPGA开发下的verilog源代码，信号发生器(DDS_AD9854_for FPGA, verilog source code, signal generator.)

用VERILOG HDL实现的任意 频率分频器源代码，是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure

应用VHDL语言将高稳晶振分频得到1pps，使用GPS的1pps信号作为触发-Application of VHDL language high stability crystal oscillator frequency to be 1pps, the use of GPS signals as a trigger of 1pps

emmc协议的实现代码，包含了SD协议，usb实现协议(The implementation code of EMMC protocol)

基于FPGA和Matlab的均衡滤波器设计与实现 基于MATLAB的数字均衡器的设计 采用FPGA实现基于LMS算法的自适应均衡器的设计研究 PWM控制的FPGA实现 等众多与FPGA、MATLAB相关的滤波器和均衡器设计 ( FPGA and MATLAB design of filter&EQ)

一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)