VHDL的您的信息的一个游戏程序的源代码，我希望那些在…

protel fpga常用封装库1，非常难找的-protel fpga library a popular package is very difficult to find the

ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。(ldpc decoding using matalb,code length 960,code rate 1/2)

these files are written in verilog but i am uploading in text format

利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现(localbus interface with PowerPC using Verilog)

DE2-70,NIOS reference file,

Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。

IC的设计可以分为两个部分，分别为：前端设计（也称逻辑设计）和后端设计（也称物理设计），这两个部分并没有统一严格的界限，凡涉及到与工艺有关的设计可称为后端设计。(The design of IC can be divided into two parts: front-end design (also called logic design) and back-end design (also known as physical design). These two parts do not have a uniform and strict boundary, and the design related to process can be called back-end design.)

modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)

uvm验证方法学入门。step by step，适合IC验证人员入门(uvm verification methodology started. step by step, for IC verification personnel entry)

Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.