VHDL的您的信息的一个游戏程序的源代码，我希望那些在…

verilog HDL verilog HDL verilog HDL -verilog HDL

在学习verilog 中与遇到一些列问题的整理。(this Documentation is about the problem about verilog which is meeted when i was learn FPGA)

program for half subtractor.

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序(A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure)

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

采用VHDL语言实现基于ＢＭ算法的ＲＳ译码器，附件为整个工程文件，内附波形仿真图。程序在QUARTUS II 9.0下仿真通过

基于FPGA实现交织 在通信中交织的算法 已在板上通过测试(based on FPGA to Interleaver)

RS码的FPGA实现，verilog语言形式，好参考资料(FPGA realization of RS code, verilog language form, a good reference)

FPGA数码管显示秒表实验 三种方法实现： 方法一： 对秒计数，得到（秒显示）0~9， 对（秒显示）计数，得到（分秒显示）0~5， 对（分秒显示）计数，得到（分钟显示）0~5， 注意进位时机 方法二： 对秒计数，得到（秒显示）0~9 对秒计数，得到（分秒显示）0~5 对秒计数，得到（分钟显示）0~5 方法三： 只对秒计数，分别取模 %60得到分钟显示 ************************ 余数%10得到分秒显示 （据说）取模运算占资源！！！！（也能接受？好像...） 再剩下的余数为秒显示 ************************(Experiment of Digital Tube Display Stopwatch Based on FPGA Three ways to achieve)

控制AD采样的程序,希望对大家能有所帮助!不对之处请多多指导!-I think it is a goog pragram ,I hope it is good for you !