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FPGA design of a full set of frequency data, I hope all of you ah like useful
FPGA设计频率计全套资料,我希望对大家啊好似有用的-FPGA design of a full set of frequency data, I hope all of you ah like useful
- 2023-01-04 19:10:03下载
- 积分:1
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CRC32_D8
crc32编码的代码(CRC32 coding code)
- 2008-05-18 21:52:39下载
- 积分:1
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XadcMicroblaze-master
用zynq实现片内的数模转换,基于最新的zynq平台(zynq xadc on FPGA arm)
- 2020-06-21 12:00:02下载
- 积分:1
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LIP4210CORE_SDIO
SDIO Verilog Sourcw code
- 2021-04-29 12:58:43下载
- 积分:1
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CPUdesign
说明: 计算机组成原理实验多时钟周期CPU设计,包含VHDL代码的设计,实验电路图,实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)
- 2020-09-07 19:28:05下载
- 积分:1
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Xilinx
说明: 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。
LDPC,
CPRI,
Turbo,
Polar,
JESD204B/C
HDMI1.4/2.0,
MIPI CSI-2,
MIPI DSI
AXI CAN
AXI USB2.0
SD Card Host
Reed-Solomon Decoder/Encoder
10G Enthernet MAC
25G Enthernet MAC
40G Enthernet MAC
50G Enthernet MAC
100G Enthernet MAC
RS Encoder/Decoder
Display Port/ DP
Video Test Pattern Generator
RapidIO
tri mode ethernet mac(LDPC,
CPRI,
Turbo,
Polar,
JESD204B/C
HDMI1.4/2.0,
MIPI CSI-2,
MIPI DSI
AXI CAN
AXI USB2.0
SD Card Host
Reed-Solomon Decoder/Encoder
10G Enthernet MAC
25G Enthernet MAC
40G Enthernet MAC
50G Enthernet MAC
100G Enthernet MAC
RS Encoder/Decoder
Display Port/ DP
Video Test Pattern Generator
RapidIO
tri mode ethernet mac)
- 2020-03-11 15:40:45下载
- 积分:1
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LaurentCPM
Laurent程序,用于CPM信号的调制,接收和分解,译码,以及判断(Laurent procedures for CPM modulation of the signal, and decomposition receiving, decoding, and to determine)
- 2013-08-16 01:32:40下载
- 积分:1
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VHDL频率计
采用VHDL编写的频率计,模块划分清晰易懂,基本原理为检测一个闸门脉冲周期内的信号次数,采用四段数码管显示
- 2022-09-17 10:05:04下载
- 积分:1
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CXFlt
通信系统中的基带信号处理中的成型滤波器代码,已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)
- 2015-03-24 09:43:05下载
- 积分:1
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DongHo
design a clock using KIT DE1
- 2014-09-19 04:46:23下载
- 积分:1