16位的移位寄存器，加上testbench,可以在modelsim里面运行~

本例是关于卷积码的一个简单算法，用verilog HDL语言编写，整个文档包括了产生卷积的整个工程。-In this case is a convolutional code on a simple algorithm, using verilog HDL language, the entire document, including the method of deconvolution of the whole project.

DESCRIPTION OF FULL ADDER

FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)

资源描述这个秒表特点是计数到59分59秒9，并且有可以让计数暂停和清零。采用了二分频，六进制和十进制组合，加上扫描电路设计而成的。

示波器的源码,基于串行口的,(oscilloscope source code, based on the serial port,)

利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion

说明：  this code works with spi and uart interfaces.

verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,

Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,

VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application