Verilog written procedures for counting frequency meter module,

4X4 KEYPAD 的密码比较模块，可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6

rs编码vvhdl 希望能通过 我不晓得具体对大家有用否 希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange

台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)

Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8-Verilog module containing a synthesizable CRC function //* polynomial: (0 1 8) //* data width: 8

this come from alter ,you can look and find it on line about h263.

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

i2c master ip for altera nios, add in qsys

altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.

dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL

利用verilog驱动LCD1602 本实验是用LCD1602显示英文。（LCD带字库）(//Use verilog driver LCD1602// video tutorial for all of us 21EDA e-learning board// The experiment is LCD1602 display in English. (LCD with font))