Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，...

基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)

LDPC encoder and decoder, very simple

使用FPGA控制AD9288，方便移植，可以拿来直接使用，适合新手学习(Use FPGA control AD9288, easy migration, can be used to directly use for novices to learn)

doulos公司出的VHDL学习工具，非常易学易懂！~(doulos company out of the VHDL learning tool, very easy to understand! ~)

AHB to Wishbone memory interface VHDL source code

《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated

一个很好的VHDL实现的功能模块程序,希望你可以用的上!-a good VHDL functional module procedures in the hope that you can use!

用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试 -Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test

说明：  基于FPGA的数字式相位测量仪的设计与制作(FPGA-Based Digital Phase Meter Design and Production)