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RS
通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2021-04-28 15:48:44下载
- 积分:1
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adder
用于实现FPGA硬件开发使用的加法器,需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)
- 2020-06-22 03:20:01下载
- 积分:1
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即使
偶数分频,包括验证程序,verilog实现,可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated
- 2022-04-22 19:15:58下载
- 积分:1
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利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用...
利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用-Realize the frequency of testing the use of FPGA-based VHDL realize, has a good test performance can be directly used
- 2022-07-06 19:40:12下载
- 积分:1
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ALTERA NIOS处理器实验,编程环境是QUARTUS,在NIOS SHELL下编译实现功能。实验USB接口...
ALTERA NIOS处理器实验,编程环境是QUARTUS,在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
- 2022-05-25 15:09:52下载
- 积分:1
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hdl-master
ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)
- 2015-08-30 21:39:28下载
- 积分:1
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8 位加法器
有一个 8 位全加器 VHDL 代码。我测试该代码在协同,看到了这段代码的工作。
- 2022-04-21 11:16:03下载
- 积分:1
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一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!...
一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
- 2023-08-19 21:45:03下载
- 积分:1
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SineGen
Basic VHDL code to create a sine wave generator for an FPGA board.
- 2014-01-24 01:04:15下载
- 积分:1
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Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) t...
实现4种常见波形正弦、三角、锯齿、方波(A、B)的频率、幅度可控输出(方波
A的占空比也是可控的),可以存储任意波形特征数据并能重现该波形,还可完成
各种波形的线形叠加输出。
-Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.
- 2022-09-08 01:55:03下载
- 积分:1