即使

利用拨码开关控制液晶显示器进行十进制数字显示。(DIP switches control the use of liquid crystal display to decimal figures.)

sram 6bit仿真模型，verilog编写(sram 6bit simulation model, verilog prepared)

以前学习VHDL语言时做的一个电子闹钟程序，可以实现时，分，秒的计时以及定时，校时，闹钟，整点报时的功能。-VHDL language before learning to do procedures in an electronic alarm clock, you can realize hours, minutes and seconds of time and from time to time, school time, alarm clock, the whole point timekeeping function.

学习DM642的开发板，适合DSP和pcb的初学者，容易上手(Learning DM642 development board)

this contain the source code for noise cancellation ,which can be used in c platform.

表决器，简单实现了表决功能，无显示功能 -vote

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

基于Xilinx Spartan6的 一个简单的CPU MU0 VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)

说明：  基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)

(7,4)循环码的verilog编码程序，（7，4）循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)