利用FPGA实现频率测试,基于VHDL实现,具有良好的测试性能可直接使用...

riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows

Vhdl实用教程，可帮助初学者迅速掌握VHDL的编写-Vhdl practical tutorials to help beginners to grasp quickly the preparation of VHDL

数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)

VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础-VHDL

主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )

1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)

VHDL 2FSK调制解调器各部分的原理与代码(The principle and code of each part of the VHDL 2FSK modem)

图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)

主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data