登录
首页 » VHDL » Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) t...

Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) t...

于 2022-09-08 发布 文件大小:9.19 kB
0 146
下载积分: 2 下载次数: 1

代码说明:

实现4种常见波形正弦、三角、锯齿、方波(A、B)的频率、幅度可控输出(方波 A的占空比也是可控的),可以存储任意波形特征数据并能重现该波形,还可完成 各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考...
    光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to
    2022-04-20 02:09:46下载
    积分:1
  • a lot of examples and test code, useful for beginners, it is easy to get started
    有很多例子及测试代码,对初学者很有帮助,很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
    2022-02-02 14:25:45下载
    积分:1
  • 一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S,用三位数码管显示。 (1) 倒计时:通
    一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S,用三位数码管显示。 (1) 倒计时:通过小键盘可以实现设定计时时间(以秒为单位,最大计时时间为99.9秒)。通过键盘实现计时开始、计时结束。当所设定的倒计时间到达00.0S后,自动停止倒计时,同时响铃。 (2) 顺计时:初始值为00.0S,通过键盘实现开始计时和结束计时功能。计时结束后,显示记录的时间。 (3) 用三个发光二极管正确显示以下状态:倒计时状态、顺计时状态、待机状态。 (4) 每当接收到有效按键时,蜂鸣器发出提示声。 顺计时在一次计时中可以记录三个不同的结束时间,并能通过按键显示三次所记录的时间。 -err
    2022-04-28 05:01:24下载
    积分:1
  • Using VHDL language driver DM128* 64LCD procedures
    用VHDL 语言驱动DM128*64LCD程序-Using VHDL language driver DM128* 64LCD procedures
    2022-07-09 01:28:22下载
    积分:1
  • Altera Sdram IP 源码,VHDL写的
    Altera Sdram IP 源码,VHDL写的-Altera Sdram IP source code, VHDL written
    2022-04-21 21:08:22下载
    积分:1
  • EP1C6_EP1C12核心板原理图,方便自己动手做板学习FPGA
    EP1C6_EP1C12核心板原理图,方便自己动手做板学习FPGA-EP1C6_EP1C12 core board schematics, do-it-yourself to do to facilitate learning FPGA board
    2022-07-11 04:51:07下载
    积分:1
  • add_verilog
    2位全加器,实现全加器的功能,有近位的加法,输出也有近位,还有testbench,进行验证,验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
    2014-05-14 18:56:33下载
    积分:1
  • Single-CPU
    说明:  简单的单周期CPU设计,实现的指令有:算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
    2020-06-16 12:28:32下载
    积分:1
  • FPGA
    用Vrilog产生一个混沌信号,并用MATLAB仿真,画出波形。(With Vrilog generate a chaotic signal simulation using MATLAB, draw the waveform.)
    2012-11-15 20:29:35下载
    积分:1
  • clock_6
    ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
    2020-06-24 12:00:02下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载