FPGA源代码

Bone microphnoe simulator. this is a trial to de-noise the bone microphone signals. This also utilizes om-lsa algorithm

基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE(RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE)

（1）MTI （2）用FFT实现MTD （3）用FIR滤波器实现MTD ((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)

VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners

一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)

SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)

说明：  多路信号复用基带系统的建模与设计,按位同步复接并掌握四路同步复接器的VHDL设计及系统的时序仿真。(library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all )