FPGA源代码

6层电梯设计，采用vhdl编写，能够实验电梯功能(6-story elevator design, using vhdl prepared, able to lift function experiments)

数字密码引爆器的输入描述：1、 在开始输入密码以前的等待状态，首先要按READY键，表示目前准备就绪，可以输入数字密码；2、 当引爆事件发生后，应该回到等待状态，设置WAIT_T键；3、 如果输入密码不正确，此时要操作READY和WAIT_T是不起作用的，必须由设计人员重新设置到等待状态，设置SETUP键，SETUP为内部按键，操作人员应该不能接触；4、 确定密码输入后，要设计一个点火按键FIRE；-digit passwords detonated"s input Description : one at the start and enter the password before the wait state, according to First READY button, now ready to be imported into digital code; Two, when detonated after the incident, should wait for the state to set up WAIT_T bond; three, if a password is not correct, this time to operate READY WAIT_T and is non-functional, the design must be re-installed to wait for the state, set up SETUP button SETUP internal keys, the operator should not contact; 4 to determine the password, to design a FIRE- ignition keys;

运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)

这是使用VHDL语言编写的密码锁程序,供大家参考-This is the use of the VHDL code lock preparation procedures for reference

我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh

vhdl的3-8译码器-instantiate the 3-8 decoder

用Verilog描述了一款简单逻辑芯片74HC595的功能该芯片功能为：带输出锁存的8位移位寄存器(use the verilog to describe a simple chip 74HC595 with 8-Bit Serial-In, Parallel-Out Shift Reg and High-Current 3-State Outputs Reg)

Z源逆变器简单升压模拟仿真。调制方式为SPWM，通过设置三角波幅值和比较电压，即可调节输出电压。(Z-source inverter simple step-up simulation. Modulation mode SPWM, by setting the the triangle amplitude and the comparison voltage to regulate the output voltage.)

说明：  xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)

用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.