VHDL参考手册，从事FPGA的好帮手，FPGA学院的终身伴侣！

FPGA中嵌入8051的核 并且实现控制128*64的液晶显示-FPGA embedded in 8051 and to achieve control of the nuclear 128* 64 LCD

用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)

多个MATLAB设计滤波器的方法程序以及图形实现(number MATLAB filter design methods and procedures and Graphics)

多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa

说明：  OFDM载波同步，Verilog编写，完全正确！！！(verilog )

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely.

基于verilog convolutional coding 的卷积编码(verilog convolutional coding )

包括很多格式的85基准电路，不需手动转换，可以供学者自行选用。(This resource including many formats 85 banchmack circuit, without manual conversion, you can choose for the scholar.)

使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现对4x4键盘的输入控制，并显示在一个8段式数码管上。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 the development board to realize 4x4 keyboard input control, and displayed in an eight-stage digital pipe.

说明：  basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)