Of PCM

出租车的计费功能的实现,计量模块、计费模块、控制模块、译码模块。(taxi fee)

8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core

显示频率测量，外接24MHz晶振，显示数据为三位，分四个档来测量-show frequency measurement, external 24MHz crystal oscillator, the data show that three, four hours to measure stalls

HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示(HDL Verilog electronic code lock input errors have prompted alarm input is correct)

vhdl program of matlab file converted to vhdl

说明：  16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)

FPGA设计中的时序分析及异步设计注意事项 (FPGA design timing analysis and design considerations for asynchronous)

说明：  数字钟通过verilog实现，并且支持Modelsim仿真(The digital clock is implemented by Verilog and supports Modelsim simulation)

快速实现HDB3码与普通码二进制码的转换，方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)

在quaters下写的比较数的大小输出，verilog语言写的，具有状态机和存储器-Written in the quaters of the size of the comparator output, verilog language written with the state machine and memory