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test-ram
design ram v8051 for project
- 2013-07-08 23:24:20下载
- 积分:1
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对视频编解码芯片ADV7181进行合理的配置,使其输出符合ITUR656标准的视频流...
对视频编解码芯片ADV7181进行合理的配置,使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656
- 2022-04-30 04:07:22下载
- 积分:1
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cntl_ddr3(xilinx)
xilinx ddr3最新VHDL代码,通过调试(xilinx ddr3 latest VHDL code through debugging)
- 2007-12-05 23:03:10下载
- 积分:1
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agc
无线通信中接收侧自动增益控制模块的vhdl代码实现(Receive side of the AGC module vhdl code for wireless communications)
- 2020-10-22 14:27:23下载
- 积分:1
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electronic-lock-and-VHDL-design
基于Max+Plus II和VHDL的电子密码锁设计(Based on Max+ Plus II electronic lock and VHDL design)
- 2011-11-17 10:19:40下载
- 积分:1
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VHDL写的串口,很好用,程序非常简单,可以调试用
VHDL写的串口,很好用,程序非常简单,可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
- 2022-08-08 18:58:10下载
- 积分:1
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正弦信号发生器(可扫频)通过验证
正弦信号发生器
正弦信号发生器(可扫频)通过验证
正弦信号发生器-Sinusoidal signal generator (which can be swept) through the validation of sinusoidal signal generator
- 2022-04-10 22:34:24下载
- 积分:1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟,计数器进行加计数,并利用数码管进行显示,当计数到9999 时,从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分:1
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SD-Host-Controller-master
说明: sd卡的verilog代码,包含一些sd卡例程(SD card Verilog code, including some SD card routines)
- 2021-04-29 13:48:42下载
- 积分:1
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hwref
spartan 3 hardware reference document xilinx
- 2009-05-22 19:10:33下载
- 积分:1