FPGA

vc707 board ucf xdc files

制作16位流水灯，实现LED模块对于拨杆0和1的识别(Making 16-bit pipeline lamp to realize the recognition of dial rod 0 and 1 by LED module)

载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring )

说明：  fpga程序，产生1pps脉冲信号，使用的verilog语言。(FPGA program generates 1 PPS pulse signal, using Verilog language.)

这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was

FPGA的仿真实例，Verilog代码编写，过程详尽，代码易懂。-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand.

用VHDL实现60秒倒计时的功能 倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)

说明：  artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)

it s vhdl program for decoder

这是一个也介绍GPIB编程的文章以及介绍GPIB协议规范-This is a GPIB programming also introduced the article and introduce GPIB norm