使用Ｖeriolog hdl 编写手机屏测试程序．

纠错和单故障检测代码使用正交拉丁方是用VHDL语言写的。

dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.

延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module

对锁相环路的仿真，二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)

用verilog 语言编译16QAM调制(a great complied code of 16QAM modulation for OFDM)

不足20元的PCI设计，含ABEL源代码。(PCI design less than 20Yuan ,including ABEL code)

fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)

自编的64B/66B编码程序，下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)

这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)

QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。(the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing. )