一种使用modelsimse6.3简单的复用方案

32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only

这个源代码可以把DE2的板子作为一个USB设备使用，以便用PC软件去控制DE2-the source code can Dictyophora the board as a USB device use, to use PC software to control DE2

这是分数阶傅里叶变换FRFT的土耳其算法的FPGA实现的程序，FPGA是Xilinx的virtecx-5，这是我在做毕业设计的时候自己编写的，希望能对你有帮助！(This is the fractional Fourier transform algorithm FRFT Turkish FPGA implementation of the program, FPGA is the Xilinx virtecx-5, which is what I was doing graduate design time I have written, I hope you can help!)

一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using

用VHDL编写的EPP通信协议，可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes

verilog例子，有130多个，值得参考，新手很有帮助-Verilog example, there are more than 130, it is also useful, very helpful to novice

基于FPGA的多电平载波移相SPWM方法实现(theCarried-Phase-shift SPWM method of Multi-Level converter based on FPGA)

vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)