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这是一个fft的IP核,安装要求为quartus6.0以上。解压安装后可在quartus里例化使用,元件主要为cyclone和stratix,最大支持1024点...
这是一个fft的IP核,安装要求为quartus6.0以上。解压安装后可在quartus里例化使用,元件主要为cyclone和stratix,最大支持1024点的转换。
- 2022-01-28 08:13:42下载
- 积分:1
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VGA_test
vga很好的学习材料,测试程序,欢迎下载(vga good learning materials, testing procedures, please download)
- 2010-08-17 22:32:45下载
- 积分:1
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利用verilog语言设计实现8路FIR滤波
利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
- 2022-01-26 16:41:16下载
- 积分:1
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calculator_final
清华大学电子课程设计:Verilog,QuartusII可正确运行,可下载到FPGA上,音乐计算器,完成两个三位数的运算,有注释,很强大!!(Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !)
- 2020-08-16 23:38:25下载
- 积分:1
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gam7
FPGA Implementation ofLow Power 64-Point
Radix-4 FFT Processor for OFDM System
- 2011-01-22 11:45:44下载
- 积分:1
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BT656_RGB
将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)
- 2021-03-22 09:29:17下载
- 积分:1
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Shumaguan
在BASYS3上实现跑马灯的功能。第一LED交替闪烁;第二LED由左至右逐个变亮,再逐个变暗;第三LED由右至左逐个变亮,再逐个变暗;第四LED由两边逐个变亮,再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)
- 2018-06-21 11:06:16下载
- 积分:1
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homework32
说明: 这是32位移位寄存器,是用verilog编写的,能够实现从1到31位的左或右的移位(This is a 32-bit shift register, is prepared verilog, can be realized from the 1-31 shift left or right)
- 2009-07-27 15:54:00下载
- 积分:1
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fir滤波器,Verilog语言写的,容易看懂
fir滤波器,Verilog语言写的,容易看懂-fir filter, Verilog language written in easy to understand
- 2023-03-26 01:30:04下载
- 积分:1
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word_aligner_8bit_test
CMV2000的对齐模块,适用于其他对齐模块,自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)
- 2020-06-16 07:00:01下载
- 积分:1