学生基本Verilog

针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

这个verilong代码实现的功能是radar processing的功能。(This verilong code function is radar processing functions.)

数字ic设计，二级缓存，格雷码，深度256，(Digital IC design, two level cache, gray code, depth 256.)

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块(RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module)

文件描述的是SDH 指针处理和系统同步代码 veriolg(SDH pointer processing and system synchronization code veriolg of file Description)

基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM

七段数码管显示的时钟程序VHDL代码 ISE编译环境(SEVEN seg VHDL ISE CLOCK)

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program