学生基本Verilog

VHDL 洗衣机程序，可实现定时、报警、洗衣，脱水等等功能。底层为VHDL文件，顶层为电路图连接

Xilinx Licenses 2018

说明：  使用vivado和Xilinx开发板实现抢答器，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)

GPS信号结构,C/A码产生方式及其测距码研究(GPS signal structure and ranging code research)

这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com

利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles

Xilinx picoBlaze explained

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

用于测试ACEX1k30的流水灯程序，晶振频率为20mhz。运行环境Maxplus2-for testing the water ACEX1k30 lights procedures, the frequency of 20MHz crystal oscillator. Operating environment FLEX10K

这是FPGA的一个简单例程，LED键盘显示程序，非常时候大家入门学习-This is the FPGA, a simple routine, LED keyboard display program, very time we started to learn