登录
首页 » VHDL » 波形发生器,带TESTBENCH, 多平台

波形发生器,带TESTBENCH, 多平台

于 2023-05-18 发布 文件大小:1.16 kB
0 124
下载积分: 2 下载次数: 1

代码说明:

波形发生器,带TESTBENCH, 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 用VHDL语言设计分频器,主要是因为一些子
    使用VHDL进行分频器设计,主要是一些分频的东西,整数分频,小数分频,奇次分频和偶次分频-Divider using VHDL to design, mainly because some sub-band stuff, integer divider, fractional-N, odd and even sub-sub-sub-sub-band frequency
    2022-04-24 21:36:07下载
    积分:1
  • A4_Led3
    说明:  led学习控制l44444444444444(led verilog led ccccccc)
    2019-05-06 09:38:14下载
    积分:1
  • assg-9-1-(lift-controller)
    Lift Controller in vhdl using process statement and state disgram
    2013-02-28 13:42:28下载
    积分:1
  • Verilog 编写的网卡DM9000A的IP核,altera公司寄的DE2系统中的源程序核...
    Verilog 编写的网卡DM9000A的IP核,altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
    2022-02-06 18:05:18下载
    积分:1
  • pingpangqiu
    基于basys2的简单的乒乓球小游戏,通过ise13.4开发,使用语言VHDL,能够通过VGA在显示屏显示,能够实现双人对打,有计分功能。(Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.)
    2014-07-04 01:42:00下载
    积分:1
  • CRC_restored
    mpeg-2 crcr32计算的代码,采用verilog编写,验证通过(mpeg-2 crcr32 caculate)
    2011-09-25 10:54:08下载
    积分:1
  • cpu_easy
    ADD MOV MOVi SUB四指令cpu设计,qutartus,(Design of four-instruction CPU)
    2019-05-13 11:44:49下载
    积分:1
  • fpga_pid
    在FPGA内使用PID算法反馈控制小车速度和方向,四电机独立(PID algorithm within the FPGA using feedback control the car speed and direction, four independent motors)
    2015-05-11 10:05:53下载
    积分:1
  • ADC
    AD转换的Matlab程序,将输入电压转换成时间(脉冲宽度信号)或频率(脉冲频率),然后由定时器/计数器获得数字值(AD conversion of the Matlab program, the input voltage is converted into a time (pulse width signal) or a frequency (pulse frequency), and then to obtain a digital value by the timer/counter)
    2012-12-18 11:01:40下载
    积分:1
  • banjian
    完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)
    2015-06-26 21:17:49下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载