波形发生器，带TESTBENCH， 多平台

VHDL TESTBENCH书写规范，对学习FPGA的同学很有帮助，掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)

USB+FPGA电路设计原理图，实际的电路板运行正常，很有参考意义。-usb_sch

用VHDL语言在FPGA上实现了fft算法和fir滤波

本设计是基于EP4CE15F17C8N和12864液晶的频率计程序(The design is based EP4CE15F17C8N and 12864 LCD frequency meter program)

VHDL语言基本数学运算库-VHDL basic arithmetic library

每次开机都将次数加1 并存储到EEPROM。这样就能直观的看到机器的使用次数 用P1口 LED做为显示，次数大于256是将溢出，按复位模拟开机 或者直接通过开关开机(Each boot will add a number of times and stored to the EEPROM. So you can visually see the frequency of use of the machine as with P1 port LED display, the number is greater than 256 will overflow, analog power or press the reset switch power directly through)

ARM+FPGA JTAG(二合一)原理图与PCB(ARM+ FPGA JTAG (combined) schematic and PCB )

这是用verilog硬件描述语言编的5分频代码-This is verilog hardware description language code is compiled by five divider

This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.