波形发生器，带TESTBENCH， 多平台

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.

super fast debounce button on vhdl, xilinx xc

I2C MASTER DESIGNED by Verilog

SPI接口测试程序，Xilinx参考设计，ML507硬件测试通过.(SPI interface test code，Xilinx reference design，tested on ML507 platform.)

直流电机控制器，属于精品vhdl源码，可在eda仿真工具上仿真实现-DC motor controller is excellent VHDL source code can be sown in simulation tools Simulation

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on

设计一个十进制计数器模块，输入端口包括 reset、up_enable 和 clk，输出端口为 count 和 bcd，当 reset 有效时（低电平），bcd 和 count 输出清零，当 up_enable 有效时（高电 平），计数模块开始计数（clk 脉冲数），bcd 为计数输出，当计数为 9 时，count 输出一 个脉冲（一个 clk周期的高电平，时间上与“bcd=9”时对齐）(Design of a decimal counter module, input port, including the reset up_enable clk, output port for the count and bcd, when reset is active (low), the bcd and count output cleared up_enable active (high), count module starts counting the (the CLK pulse number), the BCD count output when the count 9, the count output of the high level, the time of a pulse (a clk cycle with " bcd = 9" when aligned))

verilog测试，fpga测试片外sramis61lv25616，256个k个字，16位，比较难调(it is fpga is 61lv25616 simple verilog program,complete sram read and write.it can read and write .)

Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.

详细介绍了VHDL的28个程序。从简单到复杂。介绍详细-Details of the 28 procedures VHDL. From simple to complex. Detailed introduction