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VHDL版的C51核(MC8051)
VHDL版的C51核(MC8051)-VHDL version of the C51 core (MC8051)
- 2022-06-19 21:32:45下载
- 积分:1
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实现PWM波型....使用VHDL语言
实现PWM波型....使用VHDL语言-Realization of PWM waveform using the VHDL language ....
- 2022-09-10 03:00:02下载
- 积分:1
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CORDIC_vhdl
基于VHDL语言的CORDIC算法实现,用于计算sin(x),cos(x)等,实测可用(Based on VHDL CORDIC algorithm, used to calculate sin (x), cos (x), etc., the measured available)
- 2020-11-27 22:19:31下载
- 积分:1
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Continuous_acoustic_emission_board
多通道连续声发射数据采集,每个通道最大5M,采用verilog编程,内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)
- 2020-06-25 13:00:01下载
- 积分:1
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使用硬件描述语言(VHDL)的实现或门
entity or1 is(a,b:in std_logic;y:out std_logic);architecture dataflow of or1 isbeginy
- 2022-03-11 13:09:15下载
- 积分:1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分:1
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This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
这是一个用VHDL语言编写的并口转串口程序,在altera开发系统下验证通过,运用于开发板与计算机之间的通信,源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
- 2022-03-23 13:41:19下载
- 积分:1
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FPGAVHDL
vhdl例程代码大全,包含流水灯,数码管,AD,DA转换等(Guinness vhdl code routines, including water lights, digital, AD, DA conversion)
- 2020-12-17 12:19:13下载
- 积分:1
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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出,介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分:1
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FIR filter basic verilog code for implementation
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2022-07-11 03:20:47下载
- 积分:1