5. For the key to enter a password lock, assuming that reset after the seven lam...

使用CPLD进行驱动电机演示，使用硬件编程语言，适合初学者-use of motor-driven CPLD for a demonstration of the use of hardware programming language, suitable for beginners

(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

用VHDL写的一个显示程序，希望能帮上大家的忙，嘿嘿。-Written in VHDL, a display procedure, hoping that would help everyone a favor on the Hei hei.

说明：  关于计时器 verilog语言，采用arm架构的m3，可以直接应用于soc(About timer verilog language, USES the arm architecture of m3, can be directly applied to soc)

Rotary Encoder Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel. Events counter for the Rotary Encoder and displaying the events on the front panel Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).

512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。(512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.)

实现与电脑端串行数据发送与接收，波特率为9600(Realize serial data sending and receiving with the computer terminal)

SEG7数码管显示示例程序，适用于ALTERA的CPLD(SEG7 digital display sample program of ALTERA CPLD)

接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)