VHDL显示六位学好

vhdl N-0.5分频方法设计，可以输入任意数值N，即分得到N－0.5的频率。-vhdl N- 0.5-frequency method, we can input arbitrary numerical N, namely, to be N- 0.5 frequencies.

SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)

this fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga. this file contains 2,20,25,400Hz clock generating file as per required for the project.

说明：  基于fpga的数字图像处理原理及应用源码(The principle and source code of digital image processing based on FPGA)

vhdl code for internet interface

一个用VerilogHDL语言编写的多路解复用器-a Verilog HDL language used in the preparation of multi-channel demultiplexer

d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )

DS18b20 temperature sensor vhdl code

用例化语句和case语句编写的全加器的VHDL描述。-Of statements were prepared using the full adder of the VHDL description.

JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.