VHDL显示六位学好

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像增强处理,平滑,锐化,滤波(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image enhancement, smoothing, sharpening, filtering)

ahb总线Verilog代码及Verilog仿真文件(ahb bus Verilog code and Verilog simulation code)

这个是用VHDL实现FPGA对FLASH的读写。(This is achieved using VHDL FLASH FPGA to read and write.)

用VHDL语言写的，音乐演奏程序，范例歌曲为“青花瓷”片段。-Using VHDL language, and music performance procedures, examples of songs as

这是一个数字逻辑课程的电子表的实现，利用VHDL语言实现，初学者可以完全掌握，很有帮助。

Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a station in Power Save mode

此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16(this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY)

这是一个LCD1602底层驱动代码，TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)

LDPC码的FPGA实现，大家相互学习下。。(the code of LDPC implementation by FPGA)

cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program