用max+plusII编写的vhdl程序 乒乓球游戏机

cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system

说明：  点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。(ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.)

m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

一种基于FPGA的通用微处理器设计-A general-purpose FPGA-based microprocessor designs ....

说明：  很好的免费学些 verilog教程 欢迎下载(Learn a good free download verilog tutorials welcome)

在Quartus II 上编程的基于FPGA的LED显示实验(Programming in the Quartus II LED display experiment based on FPGA )

单片机与ＦＰＧＡ的通信　 功能 :单片机控制写FPGA一字节数据 单片机控制写FPGA一字节数据时钟 (注意读写数据端口可复用,也可分用) 单片机控制发送数据端口 -MCU and FPGA communication functions: SCM control FPGA to write a byte of data SCM control FPGA to write a byte of data clock (Note that the read and write data ports can be re-used, but also can be divided into use) SCM control to send data port

QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)

一个开源mips处理器verilog 源码(wishbone interface wishbone interface)