用max+plusII编写的vhdl程序 乒乓球游戏机

程序是完整的一个数字下变频器的一个Verilog程序，经测试可以使用，欢迎下载(Program is a complete Verilog program a digital down converter, tested can be used, please download)

数码管显示程序，可以显示当前的数值，可以动态显示和静态显示 可以选择显示方式-Digital tube display program can display the current value, you can dynamically display and static displays can choose to display

说明：  良好的Coding Style能减少Bug，减少锁存器出现的可能以及其他隐藏逻辑错误，也有助于减小芯片面积或所用资源(Good Coding Style can reduce Bug, reduce the possibility of latches and other hidden logic errors, and also help to reduce chip area or resources used.)

通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the description of ls138 in vhdl

This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.

用于FPGA的学习，大家值得借鉴，可以好好学习一下(this is for fpga and you can use this.)

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

说明：  对于一串二进制数前置零的计数的Verilog程序(For a string of binary zero count Verilog pre-procedure)

Generating a wider ALU from two small ones