一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合...

The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The 720-channel source driver has true 6-bit resolution, which (The SPFD5408A, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 240xRGBx320 in resolution which can be achieved by the designated RAM for graphic data. The )

it is a matrix library. it is needed for fir fier.

FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of

fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim

Actel双端口存储；通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示)

FPGA_CPLD-SHC多款FPGA CPLD开发板的原理图，很好的线路设计参考(FPGA_CPLD-SHC Variety of FPGA CPLD development board schematics, a good reference circuit design)

说明：  在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)

combinational circuits code in vhdl

fpga clock 设计，资料较好，供大家参考，非商用目的哦-fpga clock design, the information is better, for your reference, non-commercial purposes Oh

1.设计一个具有24进制计时、显示、整点报时、时间设置和闹钟功能的数字钟，要求时钟的最小分辨率时间为1s。2.多功能数字钟系统功能的具体描述如下：     计时：正常工作状态下，每日按24小时计时制计时并显示，蜂鸣器逢整点报时。     校时： 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报