供大家学习以太网VHDL和Verilog代码

a power point presentation presenting how to impliment EMF and GMF with DDS

说明：  Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes. The representation step specifies the mapping the phenotypes onto a set of genotypes. Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space. Chromosome, and individual can be used for points in the genotye space. Elements of a chromosome are called genes. A value of a gene is called an allele. Variation Operators The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

采用FPGA 来实现一个基于OFDM 技术 的通信系统中的基带数据处理部分，即调制解调器。其中发射部分的调制 器包括：信道编码（Reed-Solomon 编码），交织，星座映射，FFT 和插 入循环前缀等模块。(FPGA to implement a baseband data based on OFDM technology in the communication system processing section, namely modem. Transmitter modulator includes: channel coding (Reed-Solomon coding), interleaving, constellation mapping, FFT and insert the cyclic prefix modules.)

包括很多格式的85基准电路，不需手动转换，可以供学者自行选用。(This resource including many formats 85 banchmack circuit, without manual conversion, you can choose for the scholar.)

把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)

The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon the input signal level so that the output is at a specified Target Gain. The AGC can be configured to be either a mono or stereo input / output component. For illustration purposes, the following discussion will highlight the stereo configuration.

说明：  LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)

NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.