VHDL design language based on 8

实现verilog读写txt文件，从sut.txt从读取数据，进行操作后，写入out.txt(Realize verilog read and write txt file)

计算机组成原理课程实验使用软件，Thinpad教学机教学实验软件 实现mips代码到机器代码之间的转换 实现本机和FPGA板的通信，将机器代码送入 可在本机编写代码送入fpga板的sram中，fpga板的cpu会运行(Computer architecture course experiment using software, Thinpad teaching machine teaching experiment software mips code into machine code conversion for communication between the machine and the FPGA board can be fed into the machine code written in native code into the fpga board sram in, fpga board cpu runs)

一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows

一个游戏程序vhdl源码，供大家参考，希望有兴趣的人下载-VHDL source code of a game program for your information, I hope those who are interested in downloading

a big number class and a calculator using the class

说明：  利用FPGA实现SDH开销中帧头A1A2的检测(FPGA implementation using SDH overhead in the frame header detection of A1A2)

一个NiosII可用的LCD12864 IPcore，含例子-A NiosII available LCD12864 IPcore, with examples

这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design

vhdl code for programming

A latch3 written in VHDL.