一个latch3 VHDL编写。

STOPWATCH FPGA SEVEN SEGMENT DISPLAY

LVDS De-serialization

说明：  8通道24Bit同步A/D芯片AD7768的SPI接口例程(SPI interface routine of 8-channel 24bit synchronous A / D chip ad7768)

基于DDS的信号源设计（包括三角波、正弦波、方波）(Design of signal source based on DDS)

在ＦＰＧＡ中产生的频率可调的锯齿波型信号发生器(The frequency of the FPGA to generate the sawtooth waveform signal generator adjustable)

说明：  通过按键输入学号，并循环显示： 电路功能描述：通过Ego1上的按键输入自己的学号（8位10进制数），并存储在32位的寄存器中；8位10进制数输入完成后，实现滚动显示效果。(Enter the student number by pressing the key, and display it in a cycle: Circuit function description: input one's own student number (8-digit decimal number) through the key on ego1, and store it in 32-bit register; after the completion of 8-digit decimal number input, the scrolling display effect is realized.)

基于VHDL的1602显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL-based display program in 1602, contains the complete source code, locking pin, as well as download files documents can be directly downloaded using

verilog编程语言的讲解，有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)

说明：  用verilog编写的LVDS接口驱动程序，采用IOSERDES技术实现，经过Spartan6 FPGA调试验证，有完整的工程。(The LVDS interface driver written in verilog is implemented using IOSERDES technology. After Spartan6 FPGA debugging and verification, there is a complete project.)

FPGA做VGA通讯的详细资料，我找了很久才收集起的，很有用，可供初学者学习实用-FPGA to do VGA communication details, I am looking for a long time before starting the collection, very useful for beginners to learn practical