A NiosII available LCD12864 IPcore, with examples

GW48系统电子琴：可控制8个音节，4种音调 readme中带使用说明-GW48 system : control eight syllables, four species of taking the pitch readme use

Paint for SPARTAN 3E

使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。(Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.)

直接数字式频率合成器DDS设计、Verilog。 产生的信号可以是正弦波或方波、三角波、锯齿波等，自选。 采用DDS技术，将所需生成的波形写入ROM中，按照相位累加原理合成任意波形。 此方案得到的波形稳定，精度高，产生波形频率范围大，容易产生高频。 本实验在设计的模块中，包含以下功能： （1）通过 freq 信号输入需要的频率的值； （2）通过 wave_sel 信号选择所需的波形； （3）通过 amp_adj 信号选择波形放大的倍数。(DDS design of direct digital frequency synthesizer, Verilog. The generated signal can be sinusoidal or square wave, triangular wave, sawtooth wave and so on, optional. By using DDS technology, the required waveforms are written into ROM, and arbitrary waveforms are synthesized according to the principle of phase accumulation. The waveform obtained by this scheme is stable, accurate and easy to generate high frequency waveform. This experiment includes the following functions in the designed module: (1) Input the required frequency value through freq signal; (2) Choosing the required waveform by wave_sel signal; (3) Select the multiplier of waveform amplification by amp_adj signal.)

说明：  这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)

说明：  基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)

E1成帧器和解帧器的FPGA实现源码，测试可用(E1 Framer deframer)

说明：  adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz

基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training

FPGA读SRAM中的数再传给CY7C68013-Reading SRAM in the FPGA, then pass on a few CY7C68013