A NiosII available LCD12864 IPcore, with examples

本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 //制器，10个bit是1位起始位，8个数据位，1个结束 //位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 //现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是 //9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 //划分为8个时隙以使通信同步. //程序的工作过程是：串口处于全双工工作状态，按动key1，FPGA向PC发送“21 EDA" //字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA发送0-F的十六进制 //数据，FPGA接受后显示在7段数码管上。 //视频教程适合我们21EDA电子的所有学习板(this is a base vhdl for uart progarm.)

FFT VHDL code

Verilog HDL 读取EEPROM项目的详细构建(Verilog HDL EEPROM read the detailed construction)

this is verilog code for designing ALU in fpga.

Basic VHDL code to create a sine wave generator for an FPGA board.

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the

台湾产数字编码电位器EC11的使用测试程序(Taiwan-digital encoder potentiometer EC11 of testing procedures)

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。-VHDL hardware description language for FPGA (Cyclone II) configurations VHDL source code.

基于Verilog的数码管模拟扫描程序，分为两种显示方式，一种是数码管逐个显示，另一个是所有数码管一起显示。-Verilog-based digital control analog scanning procedures, two types of display, a digital control-by-show, and the other is with all digital tube display.

Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.