一个可以综合的Verilog 写的FIFO存储器 内附文档说明

说明：  report for a report for a class

基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)

应用背景关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。

systemc实现的一个fifo，对想要学习systemc的同学很有帮助哦(A fifo systemc achieved, the students want to learn systemc helpful oh)

this project is about FIR FIlter By VHdl codes in the ISE.

这是VHDL中计数器的代码。

描述Bayer图像无损压缩的一种先进算法及其如何在FPGA上实现(Description Bayer Image is an advanced lossless compression algorithms in the FPGA to achieve and how)

实施256点，

vhdl 加法器 vhdl 加法器 vhdl 加法器-vhdl　adder vhdl　adder vhdl　adder

4通道12位AD芯片 AD7862控制模块,VHDL源代码,适于单次转换采样,250K采样率.-4-channel 12-bit AD chip AD7862 control module, VHDL source code, suitable for single conversion sampling, 250K sampling rate.