一个可以综合的Verilog 写的FIFO存储器 内附文档说明

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

这本书主要描述了如何使用system Verilog 建立测试平台和行为级模型(This book will describe how to use the system Verilog test bench and the establishment of behavioral models)

This code implement a interation in cordic pipelline

说明：  matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

数字系统设计的入门书，教你如何学会用verilog语言实现各种数字逻辑功能，例程经典易懂(xiawenyu verilog)

基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 (32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)

[数字通信同步技术的MATLAB与FPGA实现——AlteraVerilog版]书中资源代码，非常好，分享， 希望大家下下！( U651 u0B3 u09108 u09108 u0103 u0101 u7801 uFF0C u975E u5HR U597D uFF0C u5206 u4EAB uFF0C u5E0C u671B u5927 u5BB6 u4E0B u4E0B uFF01)

Program for simulate a prtsc

这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.

verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^