一个可以综合的Verilog 写的FIFO存储器 内附文档说明

The description header can be found in signal_processing_library.h.

滤波器 Generaic FIR Filter(Generaic FIR Filter)

双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources. Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y)

LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

可生成rom.初学者可以看看。很不错的。理解后生成rom很容易的。(LPM_ROM .It is good for VHDL new learner)

Run-Length Encoder Example: Input Sequence (hexadecimal format): 0A, 14, 14, 14, 14, 14, 14, 14, 56, 56, 56, 56, 56, 32, 32, 07 Output Sequence (hexadecimal format): 0A, 14, 87, 56, 85, 32, 32, 07

该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL